The invention relates to a trench capacitor for storing an electrical charge and to a method for fabricating such a trench capacitor.
Integrated circuits (ICs) or chips contain capacitors for the purpose of storing electrical charges, such as, for example, in a dynamic random access memory (DRAM). The charge state in the capacitor represents a data bit in this case.
In order to maintain or increase international competitiveness, it is necessary to continually reduce the costs that have to be expended to realize a specific electronic function, and thus to continuously increase productivity. The continuous increase in productivity is achieved by a progressive miniaturization. This necessitates realizing an ever greater number of functions on the same chip area. This is accompanied by a continuous reduction in the size of the individual functions on the chip, so that the dimensions of the capacitors used for charge storage are also reduced.
However, the progressive miniaturization of the capacitors entails a decrease in the capacitance of the capacitors. A series of applications, such as DRAM memories for example, require a minimum storage capacitance of the storage capacitors. Therefore, it is necessary to maintain or even to increase the storage capacitance of the storage capacitors despite reduced structural dimensions. If, as is generally customary nowadays, silicon oxide is used as a capacitor dielectric, then the layer thickness of the storage dielectric would have to be reduced to a few atomic layers in future technologies. However, it is very difficult to fabricate such thin silicon oxide layers reproducibly and with sufficient accuracy, because fluctuation in the layer thickness by one atomic layer means fluctuation by more than 10%. Furthermore, it is very difficult to adequately suppress the leakage currents between two capacitor electrodes which are isolated by a storage dielectric having a thickness of a few atomic layers, since, through the effect of quantum mechanical tunneling, the charge carriers can tunnel through the potential barrier produced by the thin storage dielectric.
The prior art has already disclosed capacitors in which the storage capacitance is increased using materials such as tantalum oxide (TaO2) having a dielectric constant xcex5r=20, and also barium strontium titanate (BST, (Ba, Sr) TiO3) having an xcex5r of up to 1000 or lead zirconate titanate (PZT, Pb (Zr, Ti) O3). However, complicated and costly deposition methods are necessary for the use of BST, PZT or SBT layers, and barrier layers made of platinum (Pt), ruthenium (Ru) or ruthenium oxide (RuO2) that are difficult to process are also necessary.
The increase in the dielectric constant xcex5r through the use of TaO2 (xcex5r=20) is relatively small in comparison with NO or ONO layers, which already have a dielectric constant of xcex5r=6 to 8. Although the dielectric constant is significantly above that when BST, PZT or SBT is used, the capacitance of the capacitors is nonetheless limited by the required barrier layers with respect to silicon and polysilicon layers which serve as electrodes.
In the case of BST, PZT and SBT, it has been found that these materials belong to the materials which, chemically, cannot be etched or can be etched only with difficulty, in the case of which the etching removal, even given the use of reactive gases, is based predominantly or almost exclusively on the physical component of the etching. Due to the small or absent chemical component of the etching, the etching removal of the layer to be patterned is of the same order of magnitude as the etching removal of the mask or of the support (etching stop). Therefore, the etching selectivity with respect to the etching mask or with respect to the support is generally small, the consequence of which is that, due to the erosion of masks with inclined sidewalls and the unavoidable faceting (beveling, tapering) on the masks, only low dimensional accuracy of the patterning can be ensured. The faceting thus limits the smallest feature sizes that can be attained in the course of patterning, and also the attainable steepness of the profile sidewalls in the layers to be patterned.
Due to a lack of thermal stability, BST layers cannot, moreover, be used for processes which provide high-temperature steps after the formation of the BST layer, as is the case for example in the fabrication of DRAM memories with deep trench capacitors.
It is accordingly an object of the invention to provide a trench capacitor which overcomes the above-mentioned disadvantages of the heretofore-known trench capacitors of this general type and which provides a high storage capacitance in relation to its geometrical dimensions and has sufficient thermal stability for process steps which are carried out after its formation. It is a further object of the invention to provide a method of producing such a trench capacitor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a trench capacitor, including:
a substrate formed with a trench;
the trench having an upper region and a lower region;
an insulation collar formed in the upper region;
a buried well formed in the substrate, the lower region at least partly extending through the buried well;
a dielectric layer of tungsten oxide for lining the lower region, the dielectric layer serving as a capacitor dielectric; and
a conductive trench filling disposed in the trench.
The idea underlying the invention is the use of tungsten oxide (WOx) as a capacitor dielectric. Since tungsten oxide has dielectric constants xcex5r of greater than 50 and even greater than 300, the capacitance of the trench capacitor is increased, whilst maintaining the geometrical dimensions, by approximately 2 orders of magnitude (factor 100) if tungsten oxide is used instead of silicon oxide. The trench capacitor according to the invention has the advantage, moreover, that the installations used in semiconductor technology can likewise be used for producing tungsten oxide layers. Specially adapted and thus expensive installations, as are required for fabricating BST, PZT or SBT layers, do not have to be used. The tungsten used for producing tungsten oxide layers diffuses only very slightly into silicon, resulting in a reduced risk of contamination in the case of the trench capacitor according to the invention. The use of tungsten oxide as a capacitor dielectric is not restricted to silicon technology, however, but rather may also be used in connection with other semiconductors such as, for example, gallium arsenide (GaAs). Tungsten oxide can be used as a capacitor dielectric outside the scope of semiconductor technology as well, such as, for example, in discrete components for low-voltage and high-voltage technology. Furthermore, tungsten oxide has markedly good thermal stability up to temperatures in excess of 1100xc2x0 C. As a result, tungsten oxide can be used as a storage dielectric in memory cells having a trench capacitor, in which a transistor is formed after the trench capacitor has been fabricated, because the processing of a transistor requires, for example, thermal steps for annealing source and drain regions which are above 1000xc2x0 C.
Progressive miniaturization additionally has the consequence that the sheet resistance of capacitor electrodes continuously increases, due to the decreasing layer thickness. Therefore, in an advantageous embodiment, at least one of the capacitor electrodes is composed of tungsten or a tungsten-containing material. As a result, the resistance of the capacitor electrodes is reduced and the time needed for charging and discharging the trench capacitor is advantageously shortened.
In accordance with another feature of the invention, the conductive trench filling is a tungsten-containing material.
In a further advantageous embodiment of the invention, the tungsten-containing material is composed of tungsten silicide, tungsten nitride or of pure tungsten.
In a further advantageous embodiment of the invention, the dielectric layer forming the capacitor dielectric has a dielectric constant xcex5r greater than 50.
In accordance with another feature of the invention, a barrier layer is disposed between the dielectric layer and the substrate and/or between the dielectric layer and the conductive trench filling.
In a further advantageous embodiment of the invention, a barrier layer made of silicon oxide, silicon nitride, oxynitride, tungsten nitride, titanium nitride or tantalum nitride is formed, which is situated between the tungsten oxide layer, which forms the capacitor dielectric, and the buried plate of the capacitor, which is composed of doped silicon.
In a further advantageous embodiment of the invention, a vertical transistor is additionally situated in the trench, and serves as a selection transistor for the memory cell.
With the objects of the invention in view there is also provided, a method of producing a trench capacitor, the method includes the steps of:
introducing a buried well into a substrate;
forming a trench in the substrate, the trench having an upper region and a lower region;
forming an insulation collar in the upper region;
providing a capacitor dielectric by forming a dielectric layer of tungsten oxide lining the lower region; and
filling the trench with a conductive trench filling for providing an inner capacitor electrode.
In an advantageous fabrication method, the dielectric layer is formed by the deposition of a tungsten-containing layer, which is subsequently thermally oxidized in an oxygen-containing atmosphere.
In accordance with another mode of the invention, the tungsten-containing layer is formed from tungsten nitride, tungsten silicide or pure tungsten.
In a further advantageous embodiment of the method according to the invention, the oxidation of the tungsten-containing layer is carried out at a temperature from 200xc2x0 C. to 600xc2x0 C. in an oxygen-containing atmosphere, a water-containing atmosphere, an N2O-containing atmosphere and/or an NO is containing atmosphere.
A further advantageous fabrication method forms the dielectric layer by reactive sputtering of tungsten in an oxygen-containing atmosphere. In this case, tungsten is converted into tungsten oxide before the dielectric layer is formed.
A further advantageous embodiment of the fabrication method according to the invention carries out a thermal treatment of the dielectric layer at temperatures of between 550 and 1100xc2x0 C., with the result that the dielectric layer composed of tungsten oxide develops a dielectric constant xcex5r greater than 50.
In a further advantageous fabrication method, the tungsten-containing material of which the conductive trench filling is composed or from which a tungsten-containing layer is formed is fabricated by a CVD (Chemical Vapor Deposition) method. Furthermore, the CVD method may involve a selective CVD deposition in which tungsten is deposited selectively with respect to silicon oxide and silicon nitride on silicon. The selective CVD deposition may be carried out for example using tungsten hexafluoride (WF6) as a starting material at temperatures from 200 to 600xc2x0 C.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a trench capacitor for charge storage and a method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.